The present invention relates to a semiconductor memory device having sense amplifiers and data transfer circuits including column selection switches, and more particularly to a semiconductor memory device with means for preventing misreading of data.
FIG. 11 illustrates the circuit configuration of a sense amplifier section and a data transfer circuit section including a column selection switch in a conventional semiconductor memory device (see, for example, Japanese Laid-Open Patent Publication Nos. 5-28752 and 6-208786).
As illustrated in FIG. 11, when data is read from a selected memory cell (not shown) to a pair of bit lines BL and /BL, the potentials of the bit lines are amplified by a differential sense amplifier 1. In a case where the memory cell is a 1T1C-type cell including one transistor and one capacitor, the reference potential supplied to one of the pair of bit lines BL and /BL is amplified by the differential sense amplifier 1.
In order to activate the differential sense amplifier 1, a P-channel MOS transistor Qp1 and an N-channel MOS transistor Qn1 are turned ON by bringing a signal SA1 to a low level (“Lo”) and a signal SA2 to a high level (“Hi”), respectively. When data of “1” is read out onto the bit line BL, for example, the potential of the bit line BL is eventually brought to the power supply voltage (Vcc) level and that of the bit line /BL to the GND level through differential amplification. As a result, a P-channel MOS transistor Qp2 and an N-channel MOS transistor Qn3 are turned ON, and a P-channel MOS transistor Qp3 and an N-channel MOS transistor Qn2 are turned OFF.
Then, a column selection signal SW is brought to a high level to turn ON a pair of N-channel MOS transistors Qn4 of a column selection switch 2, whereby data read out from the memory cell is transferred to a pair of data lines DL and /DL.
FIG. 12 illustrates the potential transition of the bit lines and the data lines when data is normally transferred from the bit lines to the data lines in the conventional semiconductor memory device illustrated in FIG. 11.
As illustrated in FIG. 12, when the sense amplifier 1 is activated, the pair of bit lines BL and /BL are at the power supply voltage level and the GND level, respectively. Then, as the column selection signal SW is brought from the low level to the high level, the N-channel MOS transistors Qn4 are turned ON, whereby a charge flows from the bit line BL to the data line DL to increase the potential of the data line DL. Note that at the moment the MOS transistors Qn4 are turned ON, there occurs a charge current to the data line DL, thereby decreasing the potential of the bit line BL. However, as the potential of the data line DL increases, the charge current decreases, whereby the potential of the bit line BL increases again back to the power supply voltage level. For the data line /DL, on the other hand, a slight potential increase is observed due to the interference between the data lines. Accordingly, the potential of the bit line /BL, which is connected to the data line /DL, also increases slightly. However, the potential of the bit line /BL is eventually brought back to the GND level.
In such a conventional semiconductor memory device, data may be corrupted or misread.